1. Field of the Invention
The present invention relates to storing information in a memory, and more particularly to a system and method for storing decoded data in a memory connected to two or more data decoders.
2. Background of the Related Art
Generally, errors are generated when data is transmitted in a digital communications system. In order to correct these errors, various types of error control codes (e.g., channel codings) are used. These error control codes include a block code and a convolution code. The block code performs data coding and decoding as block units of some fixed length. Convolution coding performs coding by comparing present data to previous data using a linear shift register.
A viterbi algorithm is one type of decoding method used in convolution coding. A hardware complexity of the viterbi algorithm is increased as a square of a size of limited length (K). At present, a size of K=9 is used. Sizes higher than 9 are not used because the hardware complexity is too large. A structure of K=9 is used in CDMA (IS—95) and a viterbi code of K=9 is used with the turbo code in IMT-2000, which is the next generation mobile communication standard.
A turbo code is a code generated by connecting in parallel two recursive systematic convolution encoders (RSC) through an inner interleaver. This type of code is used in a coding method for transmitting data at high transmission rates in the next generation mobile communication standard. Turbo codes have proven to have superior coding gain to that of convolution coding. In addition, decoding for simple component codes is repeated on the receiving end, and thereby, the above method has a superior error correction function.
FIG. 1 shows a manner in which data is decoded in a mobile terminal according to the background art. The mobile terminal comprises: a receiver 10 for processing baseband data from a radio section; a memory 20 for storing received data; a central processing unit (CPU) 40 for controlling the data stored in the memory 20 so as to be inputted into a predetermined decoder; a switch 30 for switching between two decoders based on a controlling signal from the CPU 40; a viterbi decoder 50 for viterbi decoding the data input from memory 20; and a turbo decoder 60 for turbo decoding the data input from memory 20. The viterbi decoder 50 comprises a viterbi logical calculating unit 51 and a viterbi memory 52. And, the turbo decoder 60 comprises a turbo logical calculating unit 61 and a turbo memory 62.
The process of decoding data according to the background art will now be described with reference to FIG. 1. Initially, the receiver 10 receives data from an antenna (not shown) and transmits the data as frame unit to the memory 20. The memory 20 stores the frame of data transmitted from the receiver 10 as a predetermined size. When the data is stored in the memory 20, the CPU 40 identifies that the data is stored in the memory 20 and transmits a controlling signal, in the form of a decoding selection signal, to switch 30 in the decoding order indicated in next-generation specification 3GPP TS34.108. More specifically, the viterbi decoding or turbo decoding order is prescribed in specification 3GPP TS34.I08, and the viterbi decoding or the turbo decoding is performed in accordance with this specification.
If the viterbi decoding is set based on specification 3GPP TS34.108, the process will be as follows. First, the CPU 40 identifies that the viterbi decoding is set based on the specification 3GPP TS34.108, and transmits the viterbi decoding selection signal to the switch 30. Switch 30 receives the viterbi decoding selection signal, and is controlled toward the viterbi decoder 50. When the switch 30 is controlled toward the viterbi decoder 50, the CPU 40 transmits a data transmission signal to the memory 20. When the memory 20 receives the data transmission signal, it transmits the data to the viterbi decoder 50 through switch 30 which is controlled toward the viterbi decoder 50.
In a next step, the viterbi decoder 50 transmits the received data to a branch metric generator (BMG, not shown) of the viterbi logical calculating unit 51. The BMG (not shown) calculates a branch metric (BM) value from the received data, and the calculated value inputted to an add-compare-select (ACS, not shown) of the viterbi logical calculating unit 51. The BM of the BMG is a difference between a reference data generated by a state transition diagram and the transmitted data, and is defined as a hamming distance.
In a next step, the ACS (not shown) adds the BM value input from the BMG and a path metric (PM) value generated by the previous data, and transmits state transition information of smaller value to the viterbi memory 52 for the trace back decoding operation. The viterbi memory 52 stores the state transition information transmitted from the ACS (not shown) of the viterbi logical calculating unit 51, and the path data stored through the above process is traced back after a predetermined time has passed to obtain a survival path. Then, the gained survival path is stored.
When the survival path is stored in the viterbi memory 52, the viterbi decoder 50 performs decoding for the received data and stores the data in another memory (not shown).
The survival path stored in the viterbi memory 52 is used when the decoded data which is stored in another memory (not shown) is used.
If the turbo decoding is set based on the specification 3GPP TS34.108, the process will be described as follows. First, CPU 40 identifies that the turbo decoding is set based on the specification 3GPP TS34.108, and transmits a turbo decoding selection signal to switch 30. Switch 30 receives the turbo decoding selection signal and controls the switch toward the turbo decoder 60. When the switch is controlled to face the turbo decoder 60, CPU 40 transmits a data transmission signal to memory 20. In response, memory 20 transmits the data to the turbo decoder 60 through switch 30, which is controlled toward the turbo decoder 60.
In a next step, turbo decoder 60 receives the data and transmits the received data to the turbo logical calculating unit 61 in the turbo decoder 60. The turbo logical calculating unit 61 transmits a log likelihood ratio (LLR), which is gained by calculating the state transition posterior of the information included in the received data, to the turbo memory 62. The turbo memory 62 then stores the transmitted LLR.
When the LLR is stored in the turbo memory 62, the turbo decoder performs decoding for the received data, and then stores the decoded data in another memory (not shown). The LLR, which is stored in the turbo memory 62, is used when the data stored in another memory (not shown) is used.
The background art mobile terminal described above has a number of significant drawbacks. Perhaps most importantly, the background art terminal uses separated memories to perform the decoding of the viterbi decoder 50 and of the turbo decoder 60. As a result, the size of the memory requirements is as large as 256×16×4×2, and therefore a size of the terminal hardware is also increased. Further, as the size of the hardware is increased, the power consumption for driving the hardware is increased.